RFR: 8264543: Using Intel serialize instruction to replace cpuid in Cross modify fence, on supported platforms

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RFR: 8264543: Using Intel serialize instruction to replace cpuid in Cross modify fence, on supported platforms

Xubo Zhang
Intel introduced a new instruction “serialize” which ensures that all modifications to flags, registers, and memory by previous instructions are completed and all buffered writes are drained to memory before the next instruction is fetched and executed. It is a serializing instruction and can be used to implement cross modify fence (OrderAccess::cross_modify_fence_impl) more efficiently than using “cpuid” on supported 32-bit and 64-bit x86 platforms.

The availability of the SERIALIZE instruction is indicated by the presence of the CPUID feature flag SERIALIZE, bit 14 of the EDX register in sub-leaf CPUID:7H.0H.

https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

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Commit messages:
 - 8264543: Using Intel serialize instruction to replace cpuid in Cross modify fence, on supported platforms

Changes: https://git.openjdk.java.net/jdk/pull/3334/files
 Webrev: https://webrevs.openjdk.java.net/?repo=jdk&pr=3334&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8264543
  Stats: 103901 lines in 6 files changed: 103892 ins; 0 del; 9 mod
  Patch: https://git.openjdk.java.net/jdk/pull/3334.diff
  Fetch: git fetch https://git.openjdk.java.net/jdk pull/3334/head:pull/3334

PR: https://git.openjdk.java.net/jdk/pull/3334
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Re: RFR: 8264543: Cross modify fence optimization for x86

Gerard Ziemski-2
On Fri, 2 Apr 2021 23:14:44 GMT, Xubo Zhang <[hidden email]> wrote:

> Intel introduced a new instruction “serialize” which ensures that all modifications to flags, registers, and memory by previous instructions are completed and all buffered writes are drained to memory before the next instruction is fetched and executed. It is a serializing instruction and can be used to implement cross modify fence (OrderAccess::cross_modify_fence_impl) more efficiently than using “cpuid” on supported 32-bit and 64-bit x86 platforms.
>
> The availability of the SERIALIZE instruction is indicated by the presence of the CPUID feature flag SERIALIZE, bit 14 of the EDX register in sub-leaf CPUID:7H.0H.
>
> https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

If this is an optimization, do you have any numbers that show an improvement with this change?

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PR: https://git.openjdk.java.net/jdk/pull/3334