RFR(XS): 8165256: ARM64: vm/gc/concurrent/lp30yp10rp30mr0st300 Crash SIGBUS

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RFR(XS): 8165256: ARM64: vm/gc/concurrent/lp30yp10rp30mr0st300 Crash SIGBUS

Rickard Bäckman
Hi,

can I please have this small change reviewed?

We have seen crashes where it looks like a thread is seeing the call to
the interpreter stub even though it doesn't yet see the correct values
for the data and the jump.

Adding both instruction cache invalidation of the interpreter stub when
values are updated and a barrier between the stores of data/jump and the
call. This is on the ARM64 platform (_arm).

http://cr.openjdk.java.net/~rbackman/8165256/
https://bugs.openjdk.java.net/browse/JDK-8165256

Thanks
/R
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Re: RFR(XS): 8165256: ARM64: vm/gc/concurrent/lp30yp10rp30mr0st300 Crash SIGBUS

Andrew Haley
On 15/02/17 13:06, Rickard Bäckman wrote:
> Adding both instruction cache invalidation of the interpreter stub when
> values are updated and a barrier between the stores of data/jump and the
> call.

I don't think the storestore fence does anything.  ICache::invalidate_range
should flush both caches to the point of unification.

Andrew.

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Re: RFR(XS): 8165256: ARM64: vm/gc/concurrent/lp30yp10rp30mr0st300 Crash SIGBUS

Rickard Bäckman
Thank you Andrew.

I wasn't entirely sure about that. I'll remove the storestore.

On 02/15, Andrew Haley wrote:

> On 15/02/17 13:06, Rickard Bäckman wrote:
> > Adding both instruction cache invalidation of the interpreter stub when
> > values are updated and a barrier between the stores of data/jump and the
> > call.
>
> I don't think the storestore fence does anything.  ICache::invalidate_range
> should flush both caches to the point of unification.
>
> Andrew.
>

/R
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Re: RFR(XS): 8165256: ARM64: vm/gc/concurrent/lp30yp10rp30mr0st300 Crash SIGBUS

Andrew Haley
On 16/02/17 07:56, Rickard Bäckman wrote:
> Thank you Andrew.
>
> I wasn't entirely sure about that. I'll remove the storestore.

With that change the patch is OK.

Andrew.