Upgrading gcc arch ?

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Upgrading gcc arch ?

Laurent Bourgès
Hi,

I wonder if it is time to compile c/c++ code with a more recent cpu
architecture (x86-64 is quite old: only SSE ?) to take benefit of
performance optimizations offered by recent CPU and compilers (AVX...).

Of course that means such builds would be specific to a CPU class and that
will require build changes to make multiple flavors depending on the CPU
classes ...

See gcc -mtune argument:
https://gcc.gnu.org/onlinedocs/gcc-6.1.0/gcc/x86-Options.html

"
‘sandybridge’
    Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
‘ivybridge’
    Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
instruction set support.
‘haswell’
    Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
FMA, BMI, BMI2 and F16C instruction set support.
‘broadwell’
    Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE,
RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set
support.
‘skylake’
    Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and
XSAVES instruction set support.
‘bonnell’
    Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3
and SSSE3 instruction set support.
‘silvermont’
    Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set
support.
‘knl’
    Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE,
SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL,
FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F,
AVX512PF, AVX512ER and AVX512CD instruction set support.
‘skylake-avx512’
    Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set
support.

"

Comments are welcome,
Laurent
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Re: Upgrading gcc arch ?

Peter Lawrey-3
I know the drive is toward smaller builds, but it would be good to auto
select the CPU level at run time.

I suspect however, this is something the OpenJDK (or a vendor supporting
it) could do.

Perhaps code which is CPU model sensitive could be placed in a small shared
library with multiple versions and the appropriate build selected at
runtime or on installation.

Regards,
   Peter.


On 20 October 2017 at 09:19, Laurent Bourgès <[hidden email]>
wrote:

> Hi,
>
> I wonder if it is time to compile c/c++ code with a more recent cpu
> architecture (x86-64 is quite old: only SSE ?) to take benefit of
> performance optimizations offered by recent CPU and compilers (AVX...).
>
> Of course that means such builds would be specific to a CPU class and that
> will require build changes to make multiple flavors depending on the CPU
> classes ...
>
> See gcc -mtune argument:
> https://gcc.gnu.org/onlinedocs/gcc-6.1.0/gcc/x86-Options.html
>
> "
> ‘sandybridge’
>     Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
> ‘ivybridge’
>     Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
> instruction set support.
> ‘haswell’
>     Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
> FMA, BMI, BMI2 and F16C instruction set support.
> ‘broadwell’
>     Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set
> support.
> ‘skylake’
>     Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
> SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND,
> FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and
> XSAVES instruction set support.
> ‘bonnell’
>     Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3
> and SSSE3 instruction set support.
> ‘silvermont’
>     Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set
> support.
> ‘knl’
>     Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE,
> SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL,
> FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F,
> AVX512PF, AVX512ER and AVX512CD instruction set support.
> ‘skylake-avx512’
>     Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
> XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set
> support.
>
> "
>
> Comments are welcome,
> Laurent
>